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1 LTC3718 3718fa features applicatio s u descriptio u typical applicatio u low input voltage dc/dc controller for ddr/qdr memory termination n very low v in(min) : 1.5v n ultrafast transient response n true current mode control n 5v drive for n-channel mosfets eliminates auxillary 5v supply n no sense resistor required n uses standard 5v logic-level n-channel mosfets n v out(min) : 0.4v n v out tracks 1/2 v in or external v ref n symmetrical source and sink output current limit n adjustable switching frequency n t on(min) <100ns n power good output voltage monitor n programmable soft-start n output overvoltage protection n optional short-circuit shutdown timer n small 24-lead ssop package n bus termination: ddr/qdr memory, sstl, hstl, ... n servers, raid systems n distributed power systems n synchronous buck with general purpose boost the ltc ? 3718 is a high current, high efficiency synchro- nous switching regulator controller for ddr and qdr tm memory termination. it operates from an input as low as 1.5v and provides a regulated output voltage equal to (0.5)v in . the controller uses a valley current control architecture to enable high frequency operation with very low on-times without requiring a sense resistor. operating frequency is selected by an external resistor and is com- pensated for variations in v in and v out . the LTC3718 uses a pair of standard 5v logic level n-channel external mosfets, eliminating the need for expensive p-channel or low threshold devices. forced continuous operation reduces noise and rf inter- ference. fault protection is provided by internal foldback current limiting, an output overvoltage comparator and an optional short-circuit timer. soft-start capability for sup- ply sequencing can be accomplished using an external timing capacitor. opti-loop ? compensation allows the transient response to be optimized over a wide range of loads and output capacitors. efficiency vs load current , ltc and lt are registered trademarks of linear technology corporation. opti-loop is a registered trademark of linear technology corporation. no r sense is a trademark of linear technology corporation. qdr rams and quad data rate rams comprise a new family of products developed by cypress semiconductor, idt and micron technology, inc. c ss 0.1 f r c 4.75k LTC3718 c1 820pf x7r r on 237k r f1 12.1k c out : sanyo poscap 4tpb470m l1: sumida cep125-0r8mc l2: panasonic eljpc4r7mf r f2 37.4k c in2 4.7 f l2 4.7 h m2 si7440dp d2 b340a 3718 ta01 l1 0.8 h d3 mbr0520 c vcc1 10 f c b 0.33 f d b cmdsh-3 c out 470 f 2 m1 si7440dp v in 2.5v v out 1.25v 10a v in c in1 22 f 2 d1 b340a shdn boost v ref tg i on sw1 v fb1 sense + pgood pgnd1 run/ss sense i th bg sgnd1 intv cc sgnd2 v in1 v fb2 sw2 pgnd2 v in2 v out + figure 1. high efficiency bus termination supply without auxiliary 5v supply load current (a) efficiency (%) 100 90 80 70 60 50 40 30 20 10 0 0.01 1 10 100 3718 g05/ta01a 0.1 v in = 2.5v v out = 1.25v figure 1 circuit
2 LTC3718 3718fa (note 1) input supply voltage (v in2 ) .......................10v to C 0.3v boosted topside driver supply voltage (boost) ............................................... 42v to C 0.3v v in1 , i on , sw1 voltage ............................. 36v to C 0.3v run/ss, pgood voltages ......................... 7v to C 0.3v v on , v ref , v rng voltages .......(intv cc + 0.3v) to C 0.3v i th , v fb1 voltages .................................... 2.7v to C 0.3v sw2 voltage ............................................. 36v to C 0.4v v fb2 voltage ................................................. v in2 + 0.3v shdn voltage ......................................................... 10v tg, bg, intv cc peak currents .................................. 2a tg, bg, intv cc rms currents ............................ 50ma operating ambient temperature range (note 4) ................................... C 40 c to 85 c junction temperature (note 2) ............................ 125 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number LTC3718eg t jmax = 125 c, q ja = 130 c/ w the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v in1 = 15v, v in2 = 1.5v unless otherwise noted. absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics 1 2 3 4 5 6 7 8 9 10 11 12 top view g package 24-lead plastic ssop 24 23 22 21 20 19 18 17 16 15 14 13 run/ss v on pgood v rng i th sgnd1 i on v fb1 v ref shdn sgnd2 v fb2 boost tg sw1 sense + sense pgnd1 bg intv cc v in1 v in2 pgnd2 sw2 consult ltc marketing for parts specified with wider operating temperature ranges. symbol parameter conditions min typ max units buck regulator i q(vin1) input dc supply current (v in1 ) normal 1000 2000 m a shutdown supply current v run/ss = 0v 15 30 m a v fb1 feedback voltage accuracy i th = 1.2v (note 3) l C 0.65 0.1 0.65 % d v fb1(line) feedback voltage line regulation v in1 = 4v to 36v, i th = 1.2v (note 3) 0.002 %/v d v fb1(load) feedback voltage load regulation i th = 0.5v to 1.9v (note 3) l C 0.05 C 0.3 % g m(ea) error amplifier transconductance i th = 1.2v (note 3) 0.93 1.13 1.33 ms t on on-time i on = 60 m a, v on = 1.5v 200 250 300 ns i on = 30 m a, v on = 1.5v 400 500 600 ns t on(min) minimum on-time i on = 180 m a 50 100 ns t off(min) minimum off-time 300 400 ns v sense(max) maximum current sense threshold v rng = 1v, v fb1 = v ref /2 C 50mv l 108 135 162 mv v pgnd C v sw1 (source) v rng = 0v, v fb1 = v ref /2 C 50mv l 76 95 114 mv v rng = intv cc , v fb1 = v ref /2 C 50mv l 148 185 222 mv v sense(min) minimum current sense threshold v rng = 1v, v fb1 = v ref /2 + 50mv C140 C165 C190 mv v pgnd C v sw1 (sink) v rng = 0v, v fb1 = v ref /2 + 50mv C97 C115 C133 mv v rng = intv cc , v fb1 = v ref /2 + 50mv C 200 C 235 C 270 mv d v fb1(ov) output overvoltage fault threshold 8 10 12 % d v fb1(uv) output undervoltage fault threshold C 25 % v run/ss(on) run pin start threshold l 0.8 1.5 2 v v run/ss(le) run pin latchoff enable run/ss pin rising 4 4.5 v
3 LTC3718 3718fa the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v in1 = 15v, v in2 = 1.5v unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units v run/ss(lt) run pin latchoff threshold run/ss pin falling 3.5 4.2 v i run/ss(c) soft-start charge current v run/ss = 0v C 0.5 C1.2 C 3 m a i run/ss(d) soft-start discharge current v run/ss = 4.5v, v fb = 0v 0.8 1.8 3 m a v in(uvlo) v in1 undervoltage lockout v in falling l 3.4 3.9 v v in rising l 3.5 4.0 v tg r up tg driver pull-up on resistance tg high 2 3 w tg r down tg driver pull-down on resistance tg low 2 3 w bg r up bg driver pull-up on resistance bg high 3 4 w bg r down bg driver pull-down on resistance bg low 1 2 w tg t r tg rise time c load = 3300pf 20 ns tg t f tg fall time c load = 3300pf 20 ns bg t r bg rise time c load = 3300pf 20 ns bg t f bg fall time c load = 3300pf 20 ns internal v cc regulator v intvcc internal v cc voltage 6v < v in1 <30v l 4.7 5 5.3 v d v ldo(load) internal v cc load regulation i cc = 0ma to 20ma C 0.1 2% pgood output d v fb1h pgood upper threshold v fb1 = rising 8 10 12 % d v fb1l pgood lower threshold v fb1 = falling C 8 C10 C12 % d v fb1(hys) pgood hysterisis v fb1 = returning 1 2 % v pgl pgood low voltage i pgood = 5ma 0.15 0.4 v boost regulator v in2(min) minimum operating voltage 0.9 1.5 v v in2(max) maximum operating voltage 10 v i q(vin2) input dc supply current (v in2 ) normal 3 4.5 ma shutdown supply current v shdn =0v 0.01 1 m a v fb2 v fb2 feedback voltage 0 c < t < 70 c 1.205 1.23 1.255 v l 1.20 1.23 1.26 v i vfb2 v fb2 pin bias current l 27 80 na d v fb2(line) boost reference line regulation 1.5v < v in2 < 10v 0.02 0.2 %/v f boost boost switching frequency 0 c < t < 70 c 1.0 1.4 1.8 mhz l 0.9 1.4 1.9 mhz dc boost(max) boost maximum duty cycle 82 86 % i lim(boost) boost switch current limit (note 5) 500 800 ma v cesat(boost) boost switch v cesat i sw = 300ma 300 350 mv i swlkg(boost) boost switch leakage current v sw = 5v 0.01 1 m a v shdn(high) shdn input voltage high 1 v v shdn(low) shdn input voltage low 0.3 v i shdn shdn pin bias current v shdn = 3v 25 50 m a v shdn = 0v 0.01 0.1 m a
4 LTC3718 3718fa typical perfor a ce characteristics uw boost converter oscillator frequency vs temperature boost converter current limit vs duty cycle shdn pin current vs v shdn v fb2 , feedback pin voltage temperature ( c) ?0 ?5 0 25 50 75 100 switching frequency (mhz) 3718 g01 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 v in = 5v v in = 1.5v shdn pin voltage (v) 012345 shdn pin bias current ( a) 3718 g02 50 40 30 20 10 0 t a = 25 c duty cycle (%) 10 20 30 40 50 60 70 80 current limit (ma) 3718 g03 1000 900 800 700 600 500 400 300 200 70 c 25 c ?0 c temperature ( c) ?0 feedback pin voltage (v) 3718 g04 1.25 1.24 1.23 1.22 1.21 1.20 figure 1 circuit 25 0 25 50 75 100 electrical characteristics note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: t j is calculated from the ambient temperature t a and power dissipation p d as follows: LTC3718eg: t j = t a + (p d ? 130 c/w) note 3: the LTC3718 is tested in a feedback loop that adjusts v fb1 to achieve a specified error amplifier output voltage (i th ). note 4: the LTC3718 is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 5: current limit guaranteed by design and/or correlation to static test. input voltage (v) 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 v out /v in (%) 3718 g06 50.00 49.95 49.90 49.85 49.80 49.75 49.70 49.65 load = 0a load = 10a figure 1 circuit load = 1a load current (a) efficiency (%) 100 90 80 70 60 50 40 30 20 10 0 0.01 1 10 100 3718 g05/ta01a 0.1 v in = 2.5v v out = 1.25v figure 1 circuit efficiency vs load current v out /v in tracking ratio vs input voltage
5 LTC3718 3718fa typical perfor a ce characteristics uw 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 input voltage (v) frequency (khz) 3718 g07 450 400 350 300 250 200 150 100 50 0 load = 0a v out = 1.25v figure 1 circuit load = 10a load current (a) 0 1 2 3 4 5 6 7 8 910 ? v out /v out (%) 3718 g08 0 0.1 0.2 0.3 0.4 0.5 0.6 v in = 2.5v v out = 1.25v figure 1 circuit frequency vs input voltage load regulation start-up response v in = 2.5v 4ms/div 3718 g09.eps v out = 1.25v load = 0.2 w figure 1 circuit v out 1v/div i l 2a/div load-step transient v in = 2.5v 20 m s/div 3718 g10.eps v out = 1.25v load = 500ma to 10a step figure 1 circuit v out 200mv/div i l 5a/div v on voltage (v) 0 on-time (ns) 400 600 3718 g11 200 0 1 2 3 1000 i ion = 30 a 800 temperature ( c) ?0 on-time (ns) 200 250 300 25 75 3718 g12 150 100 ?5 0 50 100 125 50 0 i ion = 30 a i on current ( a) 1 10 on-time (ns) 100 1k 10k 10 100 3718 g13 v von = 0v on-time vs v on voltage on-time vs temperature on-time vs i on current
6 LTC3718 3718fa temperature ( c) ?0 3.0 run/ss threshold (v) 3.5 4.0 4.5 5.0 25 0 25 50 3718 g16 75 100 125 latchoff enable latchoff threshold temperature (c) ?0 2.0 undervoltage lockout threshold (v) 2.5 3.0 3.5 4.0 25 0 25 50 3718 g17 75 100 125 v rng (v) 0.50 maximum current sense threshold (mv) 300 250 200 150 100 50 0 0.75 1.00 1.25 1.50 3718 g18 1.75 2.00 run/ss (v) 2.0 maximum current sense threshold (mv) 3.6 2718 g19 2.8 3.0 3.2 3.4 2.2 2.4 2.6 160 140 120 100 80 60 40 20 0 temperature ( c) maximum current sense threshold (mv) 70 180 160 140 120 100 80 60 40 20 0 3718 g20 ?0 130 ?0 ?0 10 30 50 90 110 temperature ( c) gm (ms) 70 1.50 1.40 1.30 1.20 1.10 1.00 0.90 0.80 0.70 3718 g21 ?0 130 ?0 ?0 10 30 50 90 110 maximum current sense threshold vs v rng voltage maximum current sense threshold vs run/ss voltage, v rng = 1v error amplifier gm vs temperature maximum current sense threshold vs temperature, v rng = 1v typical perfor a ce characteristics uw run/ss latchoff thresholds vs temperature undervoltage lockout threshold vs temperature intv cc load current (ma) 0 ? intv cc (%) 0.2 0.1 0 40 3718 g14 0.3 0.4 0.5 10 20 30 50 temperature ( c) 50 ?5 ? fcb pin current ( a) 0 3 0 50 75 3718 g15 ? 2 1 25 100 125 pull-up current pull-down current intv cc load regulation run/ss latchoff thresholds vs temperature
7 LTC3718 3718fa uu u pi fu ctio s run/ss (pin 1): run control and soft-start input. a capacitor to ground at this pin sets the ramp time to full output current (approximately 3s/ m f) and the time delay for overcurrent latchoff (see applications information). forcing this pin below 0.8v shuts down the device. v on (pin 2): on-time voltage input. voltage trip point for the on-time comparator. tying this pin to the output voltage makes the on-time proportional to v out . the comparator input defaults to 0.7v when the pin is grounded, 2.4v when the pin is tied to intv cc . pgood (pin 3): power good output. open-drain logic output that is pulled to ground when the output voltage of the buck section is not within 10% of the regulation point. v rng (pin 4): sense voltage range input. the voltage at this pin is ten times the nominal sense voltage at maxi- mum output current and can be set from 0.5v to 2v by a resistive divider from intv cc . the nominal sense voltage defaults to 70mv when this pin is tied to ground, 140mv when tied to intv cc . i th (pin 5): current control threshold and error amplifier compensation point. the current comparator threshold increases with this control voltage. the voltage ranges from 0v to 2.4v with 1.2v corresponding to zero sense voltage (zero current). sgnd (pins 6, 11): signal ground. all small-signal com- ponents and compensation components should connect to this ground, which in turn connects to pgnd at one point. i on (pin 7): on-time current input. tie a resistor from v in to this pin to set the one-shot timer current and thereby set the switching frequency. v fb1 (pin 8): error amplifier feedback input. this pin connects the negative error amplifier input to v out . v ref (pin 9): positive input of internal error amplifier. reference voltage for output voltage, power good thresh- old, and short-circuit shutdown threshold. the output voltage is set to v ref /2. shdn (pin 10): shutdown, active low. tie to 1v or more to enable boost converter portion of the LTC3718. ground to shut down. v fb2 (pin 12): boost converter feedback. the v fb2 pin is connected to intv cc through a resistor divider to set the voltage on intv cc . set intv cc voltage according to: v intvcc = 1.23v(1 + r f2 /r f1 ) sw2 (pin 13): boost converter switch pin. connect inductor/diode for boost converter portion here. minimize trace area at this pin to keep emi down. pgnd (pins 14, 19): power ground. connect these pins closely to the source of the bottom n-channel mosfet, the (C) terminal of c vcc and the (C) terminal of c in . v in2 (pin 15): input supply pin for boost converter portion of LTC3718. must be locally bypassed. v in1 (pin 16): main input supply. decouple this pin to pgnd with at least a 1 m f ceramic capacitor. intv cc (pin 17): internal regulator output. the driver and control circuits are powered from this voltage when v in is greater than 5v. decouple this pin to power ground with a minimum of 4.7 m f low esr tantalum or ceramic capacitor. bg (pin 18): bottom gate drive. drives the gate of the bottom n-channel mosfet between ground and intv cc . sense C (pin 20): negative current sense comparator input. the (C) input to the current comparator is normally connected to power ground unless using a resistive di- vider from intv cc (see applications information). sense + (pin 21): positive current sense comparator input. the (+) input to the current comparator is normally connected to the sw node unless using a sense resistor (see applications information). sw1 (pin 22): switch node. the (C) terminal of the bootstrap capacitor c b connects here. this pin swings from a diode voltage drop below ground up to v in . tg (pin 23): top gate drive. drives the top n-channel mosfet with a voltage swing equal to intv cc superim- posed on the switch node voltage sw. boost (pin 24): boosted floating driver supply. the (+) terminal of the bootstrap capacitor c b connects here. this pin swings from a diode voltage drop below intv cc up to v in + intv cc .
8 LTC3718 3718fa fu ctio al diagra s u u w 1.4v 0.7v v rng 4 v ref 9 v on 2 + + + + + 7 i on 2.4v 0.7v 16 v in1 r on v von i ion t on = (10pf) r sq 20k i cmp i rev 5.7 a shdn switch logic bg on ov 1 240k q1 q2 0.6v 0.6v i th r c r1 40k c c1 ea ss + q5 5 r2 80k run/ss c ss 1 3718 fd01 sgnd1 6 8 run shdn 18 pgnd1 19 sense 20 pgood v fb1 3 intv cc 17 sw1 22 sense + 21 tg c b v in c in 23 boost 24 + + uv 3/10v ref 11/30v ref ov c vcc v out m2 m1 l1 c out + 0.8v ref 5v reg 1.2 a 6v d b i thb r4 40k r3 20k + + ff rq s 0.15 w sw2 driver comparator 14 shutdown shdn 10 13 + s ramp generator r c2 c c2 1.4mhz oscillator pgnd2 3718 fd02 r6 40k r10 140k r9 30k q2 x10 q1 q3 r8 (external) r7 (external) r5 40k v out2 v in2 15 v fb2 fb2 12 sgnd2 11 a2 a1 g m
9 LTC3718 3718fa main control loop the LTC3718 is a current mode controller for dc/dc step-down converters designed to operate from low input voltages. it incorporates a boost converter with a buck regulator. buck regulator operation in normal operation, the top mosfet is turned on for a fixed interval determined by a one-shot timer ost. when the top mosfet is turned off, the bottom mosfet is turned on until the current comparator i cmp trips, restart- ing the one-shot timer and initiating the next cycle. induc- tor current is determined by sensing the voltage between the sense + and sense C pins using the bottom mosfet on-resistance . the voltage on the i th pin sets the com- parator threshold corresponding to inductor valley cur- rent. the error amplifier ea adjusts this voltage by com- paring the feedback signal v fb1 from the output voltage with an internal reference generated from one half of the voltage on v ref . if the load current increases, it causes a drop in the feedback voltage relative to the reference. the i th voltage then rises until the average inductor current again matches the load current. the operating frequency is determined implicitly by the top mosfet on-time and the duty cycle required to maintain regulation. the one-shot timer generates an on- time that is proportional to the ideal duty cycle, thus holding frequency approximately constant with changes in v in . the nominal frequency can be adjusted with an external resistor r on . overvoltage and undervoltage comparators ov and uv pull the pgood output low if the output feedback voltage exits a 10% window around the regulation point. furthermore, in an overvoltage condition, m1 is turned off and m2 is turned on and held on until the overvoltage condition clears. pulling the run/ss pin low forces the controller into its shutdown state, turning off both m1 and m2. releasing the pin allows an internal 1.2 m a current source to charge up an external soft-start capacitor c ss . when this voltage reaches 1.5v, the controller turns on and begins switching, but with the i th voltage clamped at approximately 0.6v below the run/ss voltage. as c ss continues to charge, the soft- start current limit is removed. operatio u intv cc power power for the top and bottom mosfet drivers and most of the internal controller circuitry is derived from the intv cc pin. the top mosfet driver is powered from a floating bootstrap capacitor c b . this capacitor is re- charged from intv cc through an external schottky diode d b when the top mosfet is turned off. boost regulator operation the 5v power source for intv cc can be provided by a current mode, internally compensated fixed frequency step-up switching regulator that has been incorporated into the LTC3718. operation can be best understood by referring to the functional diagrams. q1 and q2 form a bandgap refer- ence core whose loop is closed around the output of the regulator. the voltage drop across r5 and r6 is low enough such that q1 and q2 do not saturate, even when v in2 is 1v. when there is no load, v fb2 rises slightly above 1.23v, causing v c (the error amplifiers output) to de- crease. comparator a2s output stays high, keeping switch q3 in the off state. as increased output loading causes the v fb2 voltage to decrease, a1s output increases. switch current is regulated directly on a cycle-by-cycle basis by the v c node. the flip-flop is set at the beginning of each switch cycle, turning on the switch. when the summation of a signal representing switch current and a ramp gen- erator (introduced to avoid subharmonic oscillations at duty factors greater than 50%) exceeds the v c signal, comparator a2 changes state, resetting the flip-flop and turn ing off the switch. more power is delivered to the output as switch current is increased. the output voltage, attenuated by external resistor divider r7 and r8, appears at the v fb2 pin, closing the overall loop. frequency com- pensation is provided internally by r c and c c . transient response can be optimized by the addition of a phase lead capacitor c pl in parallel with r7 in applications where large value or low esr output capacitors are used. as the load current is decreased, the switch turns on for a shorter period each cycle. if the load current is further decreased, the boost converter will skip cycles to main- tain output voltage regulation. if the v fb2 pin voltage is increased significantly above 1.23v, the boost converter will enter a low power state.
10 LTC3718 3718fa applicatio s i for atio wu uu a typical LTC3718 application circuit is shown in figure 1. external component selection is primarily de- termined by the maximum load current and begins with the selection of the sense resistance and power mosfet switches. the LTC3718 uses the on-resistance of the synchronous power mosfet for determining the induc- tor current. the desired amount of ripple current and operating frequency largely determines the inductor value. finally, c in is selected for its ability to handle the large rms current into the converter and c out is chosen with low enough esr to meet the output voltage ripple and transient specification. maximum sense voltage and v rng pin inductor current is determined by measuring the voltage across a sense resistance that appears between the sense + and sense C pins. the maximum sense voltage is set by the voltage applied to the v rng pin and is equal to approximately (0.13)v rng for sourcing current and (0.17)v rng for sinking current. the current mode control loop will not allow the inductor current valleys to exceed (0.13)v rng /r sense for sourcing current and (0.17)v rng for sinking current. in practice, one should allow some margin for variations in the LTC3718 and external com- ponent values and a good guide for selecting the sense resistance is: r v i sense rng out max = 10 () when v rng = 0.5 C 2v. an external resistive divider from intv cc can be used to set the voltage of the v rng pin between 0.5v and 2v resulting in nominal sense voltages of 50mv to 200mv. additionally, the v rng pin can be tied to sgnd or intv cc in which case the nominal sense voltage defaults to 70mv or 140mv, respectively. the maximum allowed sense voltage is about 1.3 times this nominal value for positive output current and 1.7 times the nominal value for nega- tive output current. connecting the sense + and sense C pins the LTC3718 can be used with or without a sense resistor. when using a sense resistor, it is placed between the source of the bottom mosfet m2 and ground. connect the sense + and sense C pins as a kelvin connection to the sense resistor with sense + at the source of the bottom mosfet and the sense C pin to pgnd1. using a sense resistor provides a well defined current limit, but adds cost and reduces efficiency. alternatively, one can eliminate the sense resistor and use the bottom mosfet as the current sense element by simply connecting the se nse + pin to the drain and the sense C pin to the source of the bottom mosfet. this improves efficiency, but one must carefully choose the mosfet on-resistance as discussed in a later section. power mosfet selection the LTC3718 requires two external n-channel power mosfets, one for the top (main) switch and one for the bottom (synchronous) switch. important parameters for the power mosfets are the breakdown voltage v (br)dss , threshold voltage v (gs)th , on-resistance r ds(on) , reverse transfer capacitance c rss and maximum current i ds(max) . the gate drive voltage is set by the 5v intv cc supply. consequently, logic-level threshold mosfets must be used in LTC3718 applications. when the bottom mosfet is used as the current sense element, particular attention must be paid to its on-resistance. mosfet on-resistance is typically speci- fied with a maximum value r ds(on)(max) at 25 c. in this case, additional margin is required to accommodate the rise in mosfet on-resistance with temperature: r r ds on max sense t ()( ) = r the r t term is a normalization factor (unity at 25 c) accounting for the significant variation in on-resistance with temperature, typically about 0.4%/ c as shown in figure 2. for a maximum junction temperature of 100 c, using a value r t = 1.3 is reasonable. the power dissipated by the top and bottom mosfets strongly depends upon their respective duty cycles and the load current. during normal operation, the duty cycles for the mosfets are:
11 LTC3718 3718fa applicatio s i for atio wu uu t v i pf on von ion = () 10 tying a resistor r on from v in to the i on pin yields an on- time inversely proportional to v in . for a step-down converter, this results in approximately constant fre- quency operation as the input supply varies: f v vr pf hz out von on = [] () 10 to hold frequency constant during output voltage changes, tie the v on pin to v out . the v on pin has internal clamps that limit its input to the one-shot timer. if the pin is tied below 0.7v, the input to the one-shot is clamped at 0.7v. similarly, if the pin is tied above 2.4v, the input is clamped at 2.4v. because the voltage at the i on pin is about 0.7v, the current into this pin is not exactly inversely proportional to v in , especially in applications with lower input voltages. to account for the 0.7v drop on the i on pin, the following equation can be used to calculate frequency: f vvv vvr pf in out von in on = - () 07 10 . ( ) to correct for this error, an additional resistor r on2 connected from the i on pin to the 5v intv cc supply will further stabilize the frequency. r v v r on on 2 5 07 = . changes in the load current magnitude will also cause frequency shift. parasitic resistance in the mosfet switches and inductor reduce the effective voltage across the inductance, resulting in increased duty cycle as the load current increases. by lengthening the on-time slightly as current increases, constant frequency operation can be maintained. this is accomplished with a resistive divider from the i th pin to the v on pin and v out . the values required will depend on the parasitic resistances in the specific application. a good starting point is to feed about 25% of the voltage change at the i th pin to the v on pin as shown in figure 3a. place capacitance on the v on pin to junction temperature ( c) ?0 r t normalized on-resistance 1.0 1.5 150 3718 f02 0.5 0 0 50 100 2.0 figure 2. r ds(on) vs temperature d v v d vv v top out in bot in out in = = the resulting power dissipation in the mosfets at maxi- mum output current are: p top = d top i out(max) 2 r t(top) r ds(on)(max) + k v in 2 i out(max) c rss f p bot = d bot i out(max) 2 r t(bot) r ds(on)(max) both mosfets have i 2 r losses and the top mosfet includes an additional term for transition losses, which are largest at high input voltages. the constant k = 1.7a C1 can be used to estimate the amount of transition loss. the bottom mosfet losses are greatest when the bottom duty cycle is near 100%, during a short-circuit or at high input voltage. operating frequency the choice of operating frequency is a tradeoff between efficiency and component size. low frequency operation improves efficiency by reducing mosfet switching losses but requires larger inductance and/or capacitance in order to maintain low output ripple voltage. the operating frequency of LTC3718 applications is deter- mined implicitly by the one-shot timer that controls the on-time t on of the top mosfet switch. the on-time is set by the current into the i on pin and the voltage at the v on pin according to:
12 LTC3718 3718fa filter out the i th variations at the switching frequency. the resistor load on i th reduces the dc gain of the error amp and degrades load regulation, which can be avoided by using the pnp emitter follower of figure 3b. inductor l1 selection given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: d= ? ? ? ? - ? ? ? ? i v fl v v l out out in 1 lower ripple current reduces cores losses in the inductor, esr losses in the output capacitors and output voltage ripple. highest efficiency operation is obtained at low frequency with small ripple current. however, achieving this requires a large inductor. there is a tradeoff between component size, efficiency and operating frequency. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . the largest ripple current occurs at the highest v in . to guarantee that ripple current does not exceed a specified maximum, the inductance should be chosen according to: l v fi v v out l max out in max = d ? ? ? ? - ? ? ? ? () () 1 once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or kool m m ? cores. a variety of inductors designed for high current, low voltage applications are available from manufacturers such as sumida, pana- sonic, coiltronics, coilcraft and toko. schottky diode d1, d2 selection the schottky diodes, d1 and d2, shown in figure 1 conduct during the dead time between the conduction of the power mosfet switches. it is intended to prevent the body diodes of the top and bottom mosfets from turning on and storing charge during the dead time, which can cause a modest (about 1%) efficiency loss. the diodes can be rated for about one half to one fifth of the full load current since they are on for only a fraction of the duty cycle. in order for the diode to be effective, the inductance between it and the bottom mosfet must be as small as possible, mandating that these components be placed adjacently. the diodes can be omitted if the efficiency loss is tolerable. c in and c out selection the input capacitance c in is required to filter the square wave current at the drain of the top mosfet. use a low esr capacitor sized to handle the maximum rms current. ii v v v v rms out max out in in out @ () 1 this formula has a maximum at v in = 2v out , where i rms = i out(max) / 2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to derate the capacitor. the selection of c out is primarily determined by the esr required to minimize voltage ripple and load step applicatio s i for atio wu uu c von 0.01 f r von2 100k r von1 30k c c v out r c v on i th LTC3718 c von 0.01 f r von2 10k q1 2n5087 r von1 3k 10k c c 3718 f03 v out intv cc r c v on i th LTC3718 (3a) (3b) figure 3. adjusting frequency shift with load current changes kool m m is a registered trademark of magnetics, inc.
13 LTC3718 3718fa applicatio s i for atio wu uu transients. the output ripple d v out is approximately bounded by: dd + ? ? ? ? v i esr fc out l out 1 8 since d i l increases with input voltage, the output ripple is highest at maximum input voltage. typically, once the esr requirement is satisfied, the capacitance is adequate for filtering and has the necessary rms current rating. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr, but can be used in cost-sensitive applications providing that consideration is given to ripple current ratings and long term reliability. ceramic capacitors have excellent low esr characteristics but can have a high voltage coeffi- cient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to signifi cant ringing. when used as input capacitors, care must be taken to ensure that ringing from inrush currents and switching does not pose an overvoltage hazard to the power switches and controller. to dampen input voltage transients, add a small 5 m f to 50 m f aluminum electrolytic capacitor with an esr in the range of 0.5 w to 2 w . high performance through-hole capacitors may also be used, but an additional ceramic capacitor in parallel is recom- mended to reduce the effect of their lead inductance. top mosfet driver supply (c b , d b ) an external bootstrap capacitor c b connected to the boost pin supplies the gate drive voltage for the topside mosfet. this capacitor is charged through diode d b from intv cc when the switch node is low. when the top mosfet turns on, the switch node rises to v in and the boost pin rises to approximately v in + intv cc . the boost capacitor needs to store about 100 times the gate charge required by the top mosfet. in most applications a 0.1 m f to 0.47 m f x5r or x7r dielectric capacitor is adequate. fault condition: current limit the maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. in the LTC3718, the maximum sense voltage is controlled by the voltage on the v rng pin. with valley current control, the maximum sense voltage and the sense resistance determine the maximum allowed inductor valley current. the corresponding output current limit is: i v r i i v r i limitpositive sns max ds on t l limitnegative sns min ds on t l =+d =-d () () () () r r 1 2 1 2 the current limit value should be checked to ensure that i limit(min) > i out(max) . the minimum value of current limit generally occurs with the largest v in at the highest ambi- ent temperature, conditions that cause the largest power loss in the converter. note that it is important to check for self-consistency between the assumed mosfet junction temperature and the resulting value of i limit which heats the mosfet switches. caution should be used when setting the current limit based upon the r ds(on) of the mosfets. the maximum current limit is determined by the minimum mosfet on- resistance. data sheets typically specify nominal and maximum values for r ds(on) , but not a minimum. a reasonable assumption is that the minimum r ds(on) lies the same amount below the typical value as the maximum lies above it. consult the mosfet manufacturer for further guidelines. minimum off-time and dropout operation the minimum off-time t off(min) is the smallest amount of time that the LTC3718 is capable of turning on the bottom mosfet, tripping the current comparator and turning the mosfet back off. this time is generally about 250ns. the minimum off-time limit imposes a maximum duty cycle of t on /(t on + t off(min) ). if the maximum duty cycle is reached,
14 LTC3718 3718fa due to a dropping input voltage for example, then the output will drop out of regulation. the minimum input voltage to avoid dropout is: vv tt t in min out on off min on () () = + output voltage programming when v fb is connected to v out , the output voltage is regulated to one half of the voltage at the v ref pin. a resistor connected between v fb and v out can be used to further adjust the output voltage according to the follow- ing equation: vv kr k out ref fb = + ? ? ? ? 60 120 if v ref exceeds 3v, resistors should be placed in series with the v ref pin and the v fb pin to avoid exceeding the input common mode range of the internal error amplifier. to maintain the v out = v ref /2 relationship, the resistor in series with the v ref pin should be made twice as large as the resistor in series with the v fb pin. applicatio s i for atio wu uu alternately, the external buffer circuit shown in figure 5 can be used. note that the bipolar devices reduce the signal swing at the mosfet gate. soft-start and latchoff with the run/ss pin the run/ss pin provides a means to shut down the LTC3718 as well as a timer for soft-start and overcurrent latchoff. pulling the run/ss pin below 0.8v puts the LTC3718 into a low quiescent current shutdown (i q < 30 m a). releasing the pin allows an internal 1.2 m a current source to charge up the external timing capacitor c ss . if run/ss has been pulled all the way to ground, there is a delay before starting of about: t v a csfc delay ss ss = m =m () 15 12 13 . . ./ when the voltage on run/ss reaches 1.5v, the LTC3718 begins operating with a clamp on i th of approximately 0.9v. as the run/ss voltage rises to 3v, the clamp on i th is raised until its full 2.4v range is available. this takes an additional 1.3s/ m f, during which the load current is folded back. during start-up, the maximum load current is re- duced until either the run/ss pin rises to 3v or the output reaches 75% of its final value. the pin can be driven from logic as shown in figure 6. diode d1 reduces the start delay while allowing c ss to charge up slowly for the soft- start function. 3.3v or 5v run/ss v in intv cc run/ss d1 (6a) (6b) d2* c ss r ss * c ss *optional to override overcurrent latchoff r ss * 3718 f06 figure 6. run/ss pin interfacing with latchoff defeated after the controller has been started and given adequate time to charge up the output capacitor, c ss is used as a short-circuit timer. after the run/ss pin charges above 4v, if the output voltage falls below 75% of its regulated value, then a short-circuit fault is assumed. a 1.8 m a cur- rent then begins discharging c ss . if the fault condition v fb1 v ref LTC3718 3718 f04 v out r fb 249k r fb 499k v ref figure 4 external gate drive buffers the LTC3718 drivers are adequate for driving up to about 30nc into mosfet switches with rms currents of 50ma. applications with larger mosfet switches or operating at frequencies requiring greater rms currents will benefit from using external gate drive buffers such as the ltc1693. q1 fmmt619 gate of m1 tg boost sw q2 fmmt720 q3 fmmt619 gate of m2 bg 10 3718 f05 intv cc pgnd q4 fmmt720 10 figure 5. optional external gate driver
15 LTC3718 3718fa persists until the run/ss pin drops to 3.5v, then the con- troller turns off both power mosfets, shutting down the converter permanently. the run/ss pin must be actively pulled down to ground in order to restart operation. the overcurrent protection timer requires that the soft- start timing capacitor c ss be made large enough to guar- antee that the output is in regulation by the time c ss has reached the 4v threshold. in general, this will depend upon the size of the output capacitance, output voltage and load current characteristic. a minimum soft-start capacitor can be estimated from: c ss > c out v out r sense (10 C4 [f/v s]) generally 0.1 m f is more than sufficient. overcurrent latchoff operation is not always needed or desired. the feature can be overridden by adding a pull- up current greater than 5 m a to the run/ss pin. the additional current prevents the discharge of c ss during a fault and also shortens the soft-start period. using a resistor to v in as shown in figure 6a is simple, but slightly increases shutdown current. connecting a resistor to intv cc as shown in figure 6b eliminates the additional shutdown current, but requires a diode to isolate c ss . any pull-up network must be able to pull run/ss above the 4.2v maximum threshold of the latchoff circuit and over- come the 4 m a maximum discharge current. intv cc supply the 5v supply that powers the drivers and internal cir- cuitry within the LTC3718 can be supplied by either an internal p-channel low dropout regulator if v in is greater than 5v or the internal boost regulator if v in is less than 5v. the intv cc pin can supply up to 50ma rms and must be bypassed to ground with a minimum of 4.7 m f tantalum or other low esr capacitor. good bypassing is necessary to supply the high transient currents required by the mosfet gate drivers. applications using large mosfets with a high input voltage and high frequency of operation may cause the LTC3718 to exceed its maximum junction tem- perature rating or rms current rating. in continuous mode operation, this current is i gatechg = f(q g(top) + q g(bot) ). the junction temperature can be estimated from the equations given in note 2 of the electrical characteristics. inductor selection for boost converter for the boost converter, the inductance should be 4.7 m h for input voltages less then 3.3v and 10 m h for inputs above 3.3v. the inductor should have a saturation current rating of approximately 0.5a or greater. a guide for select- ing an inductor for the boost converter is to choose a ripple current that is 40% of the current supplied by the boost converter. to ensure that the ripple current doesnt exceed a specified amount, the inductance can be chosen accord- ing to the following equation: l v v v if in min in max out boost = ? ? ? ? d 2 2 1 () () () diode d3 selection a schottky diode is recommended for use in the boost converter section. the motorola mbr0520 is a very good choice. boost converter output capacitor because the LTC3718s boost converter is internally com- pensated, loop stability must be carefully considered when choosing its output capacitor. small, low cost tantalum capacitors have some esr, which aids stability. however, ceramic capacitors are becoming more popular, having attractive characteristics such as near-zero esr, small size and reasonable cost. simply replacing a tantalum output capacitor with a ceramic unit will decrease the phase margin, in some cases to unacceptable levels. with the addition of a phase-lead capacitor and isolating resistor, the boost converter portion of the LTC3718 can be used success- fully with ceramic output capacitors. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in LTC3718 circuits: applicatio s i for atio wu uu
16 LTC3718 3718fa applicatio s i for atio wu uu discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. the i th pin external components shown in figure 1 will provide adequate compensation for most applications. for a detailed explanation of switching control loop theory see application note 76. design example as a design example, take a supply with the following specifications: v in = 2.5v, v out = 1.25v 100mv, i out(max) = 6a, f = 300khz. first, calculate the timing resistor with v on = v out : r vv v khz pf k on = - = 25 07 2 5 300 10 240 .. ( . )( )( ) next, use a standard value of 237k and choose the inductor for about 40% ripple current at the maximum v in : l v khz a v v h = ? ? ? ? =m 125 300 0 4 6 1 125 25 087 . ( )( . )( ) . . . selecting a standard value of 1 m h results in a maximum ripple current of: d= m ? ? ? ? = i v khz h v v a l 125 300 1 1 125 25 21 . ()() . . . next, choose the synchronous mosfet switch. choosing an irf7811a (r ds(on) = 0.013 w , c rss = 60pf, q ja = 50 c/w) yields a nominal sense voltage of: v sns(nom) = (6a)(1.3)(0.013 w ) = 101.4mv tying v rng to 1v will set the current sense voltage range for a nominal value of 100mv with current limit occurring at 133mv. to check if the current limit is acceptable, assume a junction temperature of about 10 c above a 50 c ambient with r 60 c = 1.15: i mv aa limit 3 w += 133 1 15 0 013 1 2 21 99 (. )(. ) (. ) . 1. dc i 2 r losses. these arise from the resistances of the mosfets, inductor and pc board traces and cause the efficiency to drop at high output currents. in continuous mode the average output current flows through l, but is chopped between the top and bottom mosfets. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l and the board traces to obtain the dc i 2 r loss. for example, if r ds(on) = 0.01 w and r l = 0.005 w , the loss will range from 1% up to 10% as the output current varies from 1a to 10a for a 1.5v output. 2. transition loss. this loss arises from the brief amount of time the top mosfet spends in the saturated region during switch node transitions. it depends upon the input voltage, load current, driver strength and mosfet capaci- tance, among other factors. the loss is significant at input voltages above 20v and can be estimated from: transition loss @ (1.7a C1 ) v in 2 i out c rss f 3. intv cc current. this is the sum of the mosfet driver and control currents. 4. c in loss. the input capacitor has the difficult job of filtering the large rms input current to the regulator. it must have a very low esr to minimize the ac i 2 r loss and sufficient capacitance to prevent the rms current from causing additional upstream losses in fuses or batteries. other losses, including c out esr loss, schottky diode d1 conduction loss during dead time and inductor core loss generally account for less than 2% additional loss. when making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. if you make a change and the input current decreases, then the efficiency has increased. if there is no change in input current, then there is no change in efficiency. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to d i load (esr), where esr is the effective series resistance of c out . d i load also begins to charge or
17 LTC3718 3718fa and double check the assumed t j in the mosfet: p vv v a w bot = ? ? ? ? w = 25 125 25 99 2 1 15 0 013 018 2 .. . . (. )(. ) . t j = 50 c + (0.18w)(50 c/w) = 59 c now check the power dissipation of the top mosfet at current limit with r 90 c = 1.35: p v v a v a pf khz w top = ()() w () + ()()()( )( ) = 125 25 99 135 0013 17 25 99 60 300 087 2 2 . . ... .. . . t j = 50 c + (0.87w)(50 c/w) = 93.5 c c in is chosen for an rms current rating of about 6a at temperature. the output capacitors are chosen for a low esr of 0.005 w to minimize output voltage changes due to inductor ripple current and load steps. the ripple voltage will be only: d v out(ripple) = d i l(max) (esr) = (2.6a) (0.005 w ) = 13mv however, a 0a to 6a load step will cause an output change of up to: d v out(step) = d i load (esr) = (6a) (0.005 w ) = 30mv the inductor for the boost converter is selected by first choosing an allowable ripple current. the boost converter will be operating in discontinous mode. if we select a ripple current of 170ma for the boost converter, then: l v v v ma mhz h = - ? ? ? ? =m 33 1 33 5 170 1 4 47 . . ()(.) . the complete circuit is shown in figure 7. applicatio s i for atio wu uu figure 7. design example: 1.25v/ 6a at 300khz from 2.5v c ss 0.1 f c2 100pf r c 4.75k r pg 100k run/ss v on pgood v rng i th sgnd1 i on v fb1 v ref shdn sgnd2 v fb2 boost tg sw1 sense + sense pgnd1 bg intv cc v in1 v in2 pgnd2 sw2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 LTC3718 c1 820pf r r1 10k r on 237k pgood r f1 12.1k r f2 37.4k r f3 10k r r2 39.2k c f4 1000pf c in2 4.7 f l2 4.7 h m2 irf7811a d2 b340a 3718 f07 l1 1 h d3 mbr0520 c vcc1 10 f c b 0.33 f d b cmdsh-3 c out 270 f 2 m1 irf7811a c in2 330 f v in 2.5v v out 1.25v 6a c in1 22 f 2 d1 b340a
18 LTC3718 3718fa figure 8. LTC3718 layout diagram c ss c2 r c run/ss v on pgood v rng i th sgnd1 i on v fb1 v ref shdn sgnd2 v fb2 boost tg sw1 sense + sense pgnd1 bg intv cc v in1 v in2 pgnd2 sw2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 LTC3718 c1 r on r f3 r f4 r f5 c in2 l2 bold lines indicate high current paths m2 d2 3718 f08 l1 d3 c vcc c b m1 d b v in + v out c out c in applicatio s i for atio wu uu pc board layout checklist when laying out a pc board follow one of the two suggested approaches. the simple pc board layout requires a dedicated ground plane layer. also, for higher currents, it is recommended to use a multilayer board to help with heat sinking power components. ? the ground plane layer should not have any traces and it should be as close as possible to the layer with power mosfets. ? place c in , c out , mosfets, d1 and inductor all in one compact area. it may help to have some components on the bottom side of the board. ? place LTC3718 chip with pins 13 to 24 facing the power components. keep the components connected to pins 1 to 12 close to LTC3718 (noise sensitive components). ? use an immediate via to connect the components to ground plane including sgnd and pgnd of LTC3718. use several bigger vias for power components. ? use compact plane for switch node (sw) to improve cooling of the mosfets and to keep emi down. ? use planes for v in and v out to maintain good voltage filtering and to keep power losses low. ? flood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of power component. you can connect the copper areas to any dc net (v in , v out , gnd or to any other dc rail in your system). when laying out a printed circuit board, without a ground plane, use the following checklist to ensure proper opera- tion of the controller. these items are also illustrated in figure 8. ? segregate the signal and power grounds. all small signal components should return to the sgnd pin at one point which is then tied to the pgnd pin close to the source of m2. ? place m2 as close to the controller as possible, keep- ing the pgnd, bg and sw traces short. ? connect the input capacitor(s) c in close to the power mosfets. this capacitor carries the mosfet ac current. ? keep the high dv/dt sw, boost and tg nodes away from sensitive small-signal nodes. ? connect the intv cc decoupling capacitor c vcc closely to the intv cc and pgnd pins. ? connect the top driver boost capacitor c b closely to the boost and sw pins.
19 LTC3718 3718fa one half v in , 10a bus terminator c ss 0.1 f x7r c2 100pf r c 4.75k r pg 100k run/ss v on pgood v rng i th sgnd1 i on v fb1 v ref shdn sgnd2 v fb2 boost tg sw1 sense + sense pgnd1 bg intv cc v in1 v in2 pgnd2 sw2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 LTC3718 c1 820pf x7r r on 237k pgood r f1 12.1k *sanyo poscap 4tpb470m **sumida cep125-0r8mc ***panasonic eljpc4r7mf ****sanyo poscap 6tpb330m r f2 37.4k r f3 10k c f4 1000pf x7r 4.7 f 6.3v x7r l2*** 4.7 h m2 si7440dp d2 b340a 3718 ta02 l1** 0.8 h d3 mbr0520 c vcc1 10 f 6.3v x5r c b 0.33 f x7r d b cmdsh-3 c out * 470 f 2 m1 si7440dp 22 f x5r c in2 **** 330 f v in 2.5v v out 1.25v 10a c in1 22 f x5r 2 d1 b340a + u package descriptio g package 24-lead plastic ssop (5.3mm) (reference ltc dwg # 05-08-1640) typical applicatio u information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. g24 ssop 0802 0.09 ?0.25 (.0035 ?.010) 0 ?8 0.55 ?0.95 (.022 ?.037) 5.00 ?5.60** (.197 ?.221) 7.40 ?8.20 (.291 ?.323) 1234 5 6 7 8 9 10 11 12 7.90 ?8.50* (.311 ?.335) 21 22 18 17 16 15 14 13 19 20 23 24 2.0 (.079) 0.05 (.002) 0.65 (.0256) bsc 0.22 ?0.38 (.009 ?.015) millimeters (inches) dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side * ** note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale 0.42 0.03 0.65 bsc 5.3 ?5.7 7.8 ?8.2 recommended solder pad layout 1.25 0.12
20 LTC3718 3718fa part number description comments lt ? 1613 thinsot tm step-up dc/dc converter 1.4mhz, 1.1v < v in < 10v ltc1735 high efficiency synchronous switching regulator 4v v in 36v, 0.8v v out 6v, ssop-16 ltc1772 thinsot current mode step-down controller small solution, 2.5v v in 9.8v, 0.8v v out v in ltc1773 synchronous current mode step-down controller 2.65v v in 8.5v, 0.8v v out v in , 550khz operation, > 90% efficiency ltc1778 no r sense tm synchronous step-down controller no sense resistor required, 4v v in 36v, 0.8v v out v in ltc1876 2-phase, dual synchronous step-down controller with step-up regulator 2.6v v in 36v, dual output: 0.8v v out (0.9)v in ltc3413 3a monolithic ddr memory termination regulator 3a output current, 2.25v v in 5.5v ltc3711 5-bit, adjustable, no r sense synchronous step-down controller 0.925v v out 2v, 4v v in 36v ltc3713 low input voltage, high power, no r sense synchronous controller no sense resistor required, v in(min) = 1.5v ltc3717 high power ddr memory termination regulator 4v v in 36v, v out tracks v in or v ref , i out from 1a to 20a ltc3778 no r sense synchronous step-down controller optional sense resistor, 4v v in 36v, 0.6v v out v in ltc3831 high power ddr memory termination regulator v out tracks 1/2 v in or v ref , 3v v in 8v, i out from 1a to 20a no r sense and thinsot are trademarks of linear technology corporation. ? linear technology corporation 2002 lt/tp 1103 1k rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com related parts c ss 0.1 f x7r c2 100pf r c 10k r pg 100k run/ss v on pgood v rng i th sgnd1 i on v fb1 v ref shdn sgnd2 v fb2 boost tg sw1 sense + sense pgnd1 bg intv cc v in1 v in2 pgnd2 sw2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 LTC3718 c1 3300pf x7r r on 237k pgood r ref 499k r fb 249k r f1 12.3k *sanyo poscap 4tpb470m **toko d104c ***panasonic eljpc4r7mf ****kemet t495x336k025as r f2 107k r f3 10k c f4 200pf x7r c in2 22 f x5r l2*** 10 h m2 si7440dp d2 b340a 3718 ta03 l1** 1.8 h d3 mbr0520 c vcc2 4.7 f c f 0.1 f c vcc1 4.7 f x5r c b 0.33 f x7r d b cmdsh-3 c out * 470 f 2 m1 si7440dp c in1 **** 33 f 2 25v v in 6v to 24v v out1 2.5v 10a v out2 12v 130ma v in2 5v d1 b340a r f 1 + dual output 2.5v, 10a buck converter and 5v to 12v/130ma boost converter typical applicatio u

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